Improving ASIC verification using Parameterized FPGA Configurations Ghent University
As MooreU+2019 Law continues to drive the number of transistors inside integrated circuits (IC) higher, alongside the scaling down of transistor dimensions, more complex digital designs are being realized. Continuous technology evolution has led to increasingly more complex architectures and designs. Verifying and validating these designs has become an increasingly difficult task. Additionally, multiple designs contain a safety-critical ...