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Onderzoeker
Geert Hellings
- Disciplines:Nanotechnologie, Ontwerptheorieën en -methoden
Affiliaties
- Geassocieerde Afdeling ESAT - INSYS (INSYS), Integrated Systems (Afdeling)
Lid
Vanaf1 aug 2020 → 31 dec 2011 - Elektronische Circuits en Systemen (ECS) (Afdeling)
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Vanaf1 aug 2020 → 30 nov 2011 - Geassocieerde Afdeling ESAT - INSYS, Integrated Systems (Afdeling)
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Vanaf19 nov 2007 → 31 dec 2011 - Departement Elektrotechniek (ESAT) (Departement)
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Vanaf16 apr 2005 → 18 nov 2007
Publicaties
1 - 10 van 74
- Strained c:Si0.55Ge0.45 with embedded e:Si0.75Ge0.25 S/D IFQW SiGe-pFET for DRAM periphery applications(2016)
Auteurs: Geert Hellings
Pagina's: 255 - 258 - Impact of local interconnects on ESD design(2015)
Auteurs: Shih-Hung Chen, Geert Hellings, Roman Boschke
Aantal pagina's: 4 - On and off state Hot Carrier reliability in Junctionless high-K MG gate-all-around nanowires(2015)
Auteurs: Geert Hellings, Hiroaki Arimura, Jacopo Franco
Pagina's: 366 - 369 - ESD protection diodes in optical interposer technology(2015)
Auteurs: Roman Boschke, Guido Groeseneken, Shih-Hung Chen, Geert Hellings
Pagina's: 1 - 4 - Characterization of self-heating in high-mobility Ge FinFET pMOS devices(2015)
Auteurs: Geert Hellings, Guido Groeseneken
Pagina's: 60 - 61 - ESD characterization of gate-all-around (GAA) Si nanowire devices(2015)
Auteurs: Shih-Hung Chen, Geert Hellings, Roman Boschke, Guido Groeseneken
Pagina's: 362 - 365 - VFTLP characteristics of ESD protection diodes in advanced bulk FinFET technology(2015)
Auteurs: Shih-Hung Chen, Geert Hellings, Roman Boschke, Guido Groeseneken
Pagina's: 9 - 1 - Gate-All-Around NWFETs vs. Triple-Gate FinFETs: Junctionless vs. Extensionless and Conventional Junction Devices with Controlled EWF Modulation for Multi-VT CMOS(2015)
Auteurs: Geert Hellings
Aantal pagina's: 2 - ESD characterization of planar InGaAs devices(2015)
Auteurs: Roman Boschke, Geert Hellings, Shih-Hung Chen, Ali Reza Alian, Jacopo Franco, Guido Groeseneken
Pagina's: 3 - Local CDM ESD protection circuits for cross-power domains in 3D IC applications(2014)
Auteurs: Shih-Hung Chen, Geert Hellings, Roman Boschke, Guido Groeseneken
Pagina's: 781 - 783
Patenten
1 - 5 van 5
- Method for fabricating finfet technology with locally higher fin-to-fin pitch (Inventor)
- Breakdown-based physical unclonable function (Inventor)
- Breakdown-based physical unclonable function (Inventor)
- Scalable quantum well device and method for manufacturing the same (Inventor)
- IMPLANT FREE QUANTUM WELL TRANSISTOR, METHOD FOR MAKING SUCH AN IMPLANT FREE QUANTUM WELL TRANSISTOR AND USE OF SUCH AN IMPLANT FREE QUANTUM WELL TRANSISTOR (Inventor)