High performance and low power three-dimensional static random access memory and method of forming same.

A three-dimensional (3D) static random access memory (SRAM) cell includes two PU transistors arranged in a first tier, two PD transistors arranged in a second tier positioned above or below the first tier, and two PG transistors arranged in the first or second tier. The transistors can be fin transistors, and each PU and PD transistor can have a first and second number of fins, respectively. The transistors can also be nanosheet-based transistors, and each PU and PD transistor can have a first and a second nanosheet width, respectively.

Octrooi-publicatienummer: US20240373617A

Bron: USPTO

Jaar van publicatie: 2024

Status: Aangevraagd

Technologiedomeinen: undefined