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Process-Induced Power-Performance Variability in Sub-5nm III-V Tunnel FETs

Tijdschriftbijdrage - Tijdschriftartikel

We examine the power-performance variability of a projected sub-5-nm GaAsSb/InGaAs vertical tunnel FET considering various process control tolerances in the state-of-the-art device integration and propose countermeasures in device design. Nominal and three-sigma-corner device characteristics generated in quantum-mechanical/TCAD simulations are used to calibrate a semiempirical compact model, based on which the nominal and variability-inclusive energy-delay landscapes are extracted from ring-oscillator circuit simulations at sub-500-mV supply voltages. Variations in four parameters are identified as of major impact on the worst-case speed loss and iso-speed energy penalty: dopant pocket thickness, gate work function, hetero-band offset, and body thickness (in descending order). Variability-resilient device options are explored against pocket thickness variation, including: 1) pocket desensitization with increased thickness and reduced doping concentration and 2) broken-gap tunnel FET with a negative effective band gap. Reengineered devices achieve <18x speed loss and <3x energy penalty for (0.1-1) ns gate delay with respect to the nominal corner.
Tijdschrift: IEEE Transactions on Electron Devices
ISSN: 0018-9383
Issue: 6
Volume: 66
Pagina's: 2802 - 2808
BOF-keylabel:ja
IOF-keylabel:ja
BOF-publication weight:1
Authors from:Government, Higher Education
Toegankelijkheid:Open