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Test set generation almost for free using a Run-Time FPGA reconfiguration technique Universiteit Gent
The most important step in the final testing of fabricated ASICs or the functional testing of ASIC and FPGA designs is the generation of a complete test set that is able to find the possible errors in the design. Automatic Test Pattern Generation (ATPG) is often done by fault simulation which is very time-consuming. Speed-ups in this process can be achieved by emulating the design on an FPGA and using the actual speed of the hardware ...
Effective and Efficient Test and Diagnosis Pattern Generation for Many Inter-Die Interconnects in Chiplet-Based Packages Interuniversitair Micro-Electronica Centrum vzw
Chiplet-based (2.5D and 3D) multi-die packages implement large amounts of inter-die interconnects with micro-bump connections and possibly TSVs. These interconnects can be subject to manufacturing defects. The most common defects are shorts and opens, which occur both in hard and weak (= resistive) variants. Traditional interconnect automatic test pattern generation (I-ATPG) methods only cover hard defects. These methods are generally considered ...
Automatic test signal generation for mixed-signal integrated circuits using circuit partitioning and interval analysis KU Leuven
© 2016 IEEE. A method is presented to address the automatic generation of test signals for analog and mixed-signal integrated circuits. No restriction on the number of inputs or the nonlin-earity of the circuit are made. The circuit under consideration is first decomposed into a set of sub-circuits, called blocks, in order to break down the complexity of the problem. The effect of a targeted fault is then automatically analyzed at the transistor ...
Towards a framework for constraint-based test case generation KU Leuven
In this paper, we propose an approach for automated test case generation based on techniques from constraint programming (CP). We advocate the use of standard CP search strategies in order to express preferences on the generated test cases and to obtain the desired degree of coverage. We develop our framework in the concrete context of an imperative language and show that the technique is sufficiently powerful to deal with arbitrary ...
Automatic generation of test infrastructures for analog integrated circuits by controllability and observability co-optimization KU Leuven
© 2016 Elsevier B.V. This paper presents a method to address the automatic testing of analog ICs for catastrophic defects. Based on Design-for-Testability building blocks offering extra controllability and extra observability, a test infrastructure is generated for a targeted circuit. The selection of the extra blocks and their insertion into the circuit is done automatically by a workflow based on DC simulations and optimization algorithms. ...
Random test generation from regular expressions for graphical user interface (GUI) testing Universiteit Antwerpen
Generation of test sequences, that is, (user) inputs - expected (system) outputs, is an important task of testing of graphical user interfaces (GUI). This work proposes an approach to randomly generate test sequences that might be used for comparison with existing GUI testing techniques to evaluate their efficiency. The proposed approach first models GUI under test by a finite state machine (FSM) and then converts it to a regular expression ...
Regular expression based test sequence generation for HDL program validation Universiteit Antwerpen
This paper proposes a test sequence generation approach for behavioral model validation of sequential circuits implemented in Hardware Description Language (HDL). In the procedure of test sequence generation proposed in this study, Regular Expressions (REs) are utilized to model the behavior of the System Under Test (SUT). First, the HDL program is converted to a Finite State Machine (FSM). Then, the obtained FSM is transformed to RE which is ...
Parameterised FPGA reconfigurations for efficient test set generation Universiteit Gent
This paper proposes the use of parameterised FPGA configurations for a new test set generation approach. The time-consuming problem of test set generation aims at finding the right input values to fully test an ASIC design. Since well-known methods for test set generation such as fault simulation techniques have become impractical to use due to their speed limitations, FPGAs have been used in order to facilitate fault injection techniques. ...
ADAGE: Automatic DfT-Assisted Generation of Test Stimuli for Mixed-Signal Integrated Circuits KU Leuven
© 2013 IEEE. This paper presents an integrated workflow for design-for-test and test signal generation of mixed-signal circuits. The DfT phase pre-partitions the core under test and allows an efficient automatic generation of test signals.-Hans-Joachim Wunderlich, Universität Stuttgart.