Analog in-memory computing based inference accelerator Interuniversitair Micro-Electronica Centrum vzw
A compute cell (10) for in-memory multiplication of a digital data input (X) and a balanced ternary weight (w) is disclosed and an in-memory computing device comprising an array thereof. The compute cell comprises a set of input connectors (11a, 11b) for receiving modulated input signals (A+, A-) representative of a sign and a magnitude of the digital data input, and a memory unit (12) configured for storing the balanced ternary weight. A logic unit (13) of the compute cell is connected to the set of input connector and the memory unit (12) to receive the data input and the balanced ternary ...