Improvements in or relating to analog-to-digital converters. Interuniversitair Micro-Electronica Centrum vzw
Described herein is a SAR DAC architecture which uses two parallel DACs (200a, 200b) for performing the comparison and feedback simultaneously. While one DAC executes a feedback step, the output of the other DAC is used as input for a comparator (210a, 210b). For fast operation, the comparator performs the comparison with reference voltage that has a positive or negative offset from a mid-scale value. The sign of the offset is determined by the previous comparison. As a result, the same delay can be used for each DAC feedback and comparison step, reducing the total conversion time to the time ...