A vertical isolated gate field effect transistor integrated in a semiconductor chip. Interuniversitair Micro-Electronica Centrum vzw
A vertical isolated gate FET transistor according to the invention is integrated in the front end of line of a semiconductor chip. The transistor includes a modified version of a buried power rail and back side TSV (Through Semiconductor Via) connection known for connecting the front end of line to a back side signal delivery network, such as a power delivery network (PDN), the PDN being arranged on the backside of the semiconductor substrate that carries the active devices of the FEOL on its front side. As opposed to a standard power rail/TSV combination, the TSV is not electrically ...