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A 94.6%-Efficiency Fully Integrated Switched-Capacitor DC-DC Converter in Baseline 40nm CMOS Using Scalable Parasitic Charge Redistribution

Book Contribution - Book Chapter Conference Contribution

© 2016 IEEE. In recent years, there has been an ever-increasing interest in monolithic power supplies. Integrating the power supply with the application has many direct benefits, including a reduction of the bill of materials and reduced size. Even more substantial are the potential efficiency gains due to reduced power delivery network losses and voltage margins, especially in a world dominated by energy limited devices where this translates directly into improved battery life. However, to warrant a migration to integrated power supplies, it is crucial that these gains do not get eclipsed by the decreased efficiency of the power converter caused by the reduced quality of integrated passives. Switched-Capacitor (SC) converters have become more and more popular because, contrary to inductive converters, they only use transistors and capacitors, both of which are native to CMOS technologies and scale well into deep-submicron nodes. The maximal efficiency of an SC converter depends on two factors [1]: a topological parameter whose optimal value depends on the Voltage Conversion Ratio (VCR), and a, the relative size of the parasitic, so-called Bottom-Plate (BP), capacitance to the flying capacitance. The further the VCR is removed from 1/1 and the larger a, the lower the efficiency that is obtained. With a typically around 1.5% for MOM- and MIM-, and 7% for MOS capacitors, an SC converter could theoretically achieve an efficiency of 89% and 79% respectively for a 1/2 conversion [1]. Due to additional losses (control, leakage, etc.), this efficiency ceiling is lower, but its existence is still confirmed by previous work. The highest reported monolithic SC converter efficiencies in baseline CMOS are 87% [2], although at a more favorable VCR of 4/5, and 85% [3], both using MIM capacitors. Higher efficiencies have been demonstrated using high-density Deep-Trench (90%) [4] or Ferro-Electric (91% in 1/2) [5] capacitors, which have reportedly up to 25 times smaller α. However, these capacitors are not part of baseline CMOS and thus require additional masks and costs.
Book: Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Pages: 220 - 221
ISBN:9781467394666
Publication year:2016
BOF-keylabel:yes
IOF-keylabel:yes
Authors from:Higher Education
Accessibility:Open