III-V on Si Nano-ridge photodiodes for SWIR applications

III-V compound semiconductors are widely used in numerous applications, such as optoelectronics, communication systems, photovoltaics, etc. In order to achieve a cost-effective integration of III-V with CMOS circuitry, hybrid III-V/CMOS technology is required. Monolithic integration of III-V material on 300 mm Si with CMOS using NR engineering is one of the integration approaches to achieve this. Such hybrid technology utilizes the heteroepitaxy process, which by its nature leads to defect formation in the device stack. Due to significant impact of these defects on the electro-optic performance of the devices, it is important to gain a better understanding of various physical phenomena which drive the potential device degradation. 

This work, therefore, concentrates on comprehensive investigation of defects by using physical and electrical characterization techniques. This understanding is applied to explain the observed electrical performance of GaAs and InGaAs nano-ridge diodes. A methodology to extract the surface state density and bulk traps from the DLTS spectrum is developed and used for defect characterization of III-V NR diodes. It is observed that III-V NR-based diodes show presence of bulk defects such as point defects, threading dislocations  and surface states. The origin of these defects and  its impact on the mechanism of the leakage current is studied. The point defects are attributed to a complex of As antisite or an As interstitial and substitutional oxygen in place of As  with energy level  0.8+- 0.03 eV and 0.53+- 0.03 eV below conduction band, respectively. For devices with lower trench aspect ratio (<2), threading dislocations become dominant for the leakage current. Moreover, the energy level of the surface states is determined to be  for NR based devices, which is attributed to the dangling bonds created by Ga-vacancies on the surface or to additional impurities. Based on the experimentally extracted activation energy 0.1 eV< Eact< Eg/2, the leakage current is predicted to be a dominated by the trap-assisted tunnelling (TAT) component for the NR devices. This correlation is confirmed by the physics based TCAD device model, calibrated by using experimental I-V and C-V data. Additionally, a study of contact resistivity for various III-V layers (p,n,-GaAs, p,n-InGaAs, p-GaAsSb) is performed to improve the contact resistance and thus the electrical performance of the NR-based devices.  The contact resistivity dependence on the indium fraction in InGaAs is also reported. 

The results of defects, leakage current and contact resistance analysis presented in this work provides a good understanding of NR based diodes and their electrical performance for the given defect densities in the device stack. This helps in the development of efficient and cost-effective hybrid III-V/Si devices for future applications.