CIRCUIT FOR DIGITIZING SUM OF INPUT SIGNALS IN MULTI-BIT SINGLE-LOOP FEED-FORWARD SIGMA-DELTA MODULATOR IN ANALOG-TO-DIGITAL CONVERTER, HAS QUANTIZER COMPRISING LOGIC BLOCK FOR DETERMINING REPRESENTATION OF SUM FROM COMPARATOR OUTPUT SIGNAL

The present invention relates to a circuit for digitizing a sum of at least one first input signal and a plurality of second input signals comprising \n - a passive adder circuit arranged for performing a summation of the second input signals and for outputting a summation signal, \n - a multi-bit quantizer circuit comprising a comparator arranged for comparing said summation signal applied at a first comparator input terminal with a signal applied at a second comparator input terminal, said signal being derived from the at least one first input signal and having an appropriate polarity so that the difference between the summation signal and said signal at the second comparator input terminal is indicative of the sum of the at least one first input signal and the plurality of second input signals, wherein the comparator is further arranged for producing a comparator output signal based on the sum of the at least one first input signal and the plurality of second input signals. The multi-bit quantizer circuit further comprises a control logic block for determining a multi-bit representation of the sum from the comparator output signal.

Patent Publication Number: EP2706666

Year filing: 2012

Year approval: 2015

Year publication: 2014

Status: Requested

Technology domains: Basic communication processes

Validated for IOF-key: Yes

Attributed to: Associatie KULeuven