Decreasing the critical dimensions in integrated circuits

A method for lithographic patterning of a substrate is described. The method comprises obtaining a substrate to be patterned. It further comprises subsequently performing at least twice the following cycle: applying a lithographical patterning process of a thermally shrinkable metal-oxide layer for forming a metal-oxide pattern, and thermally shrinking the metal-oxide pattern. The different metal oxide patterns formed during the at least two cycles are positioned in proximity to each other such that the shrunk metal-oxide patterns form together an overall pattern to be transferred to the substrate. After performing the cycle at least twice, the overall pattern is transferred to the substrate.

Patent Publication Number: US9406503

Year filing: 2015

Year approval: 2016

Year publication: 2016

Status: Assigned

Technology domains: Semiconductors

Validated for IOF-key: Yes

Attributed to: Associatie KULeuven