Modelling, exploration and technology assessment of steep-subthreshold-slope transistors for N5/N3 CMOS power-performance scaling
As CMOS scales down to N5 node and beyond, gate length scaling becomes increasingly difficult if not impossible. The combined challenge of gate and contact scaling has highlighted the need for innovation in device architecture and circuit design imperative. The use of ambipolar devices, vertical devices, 2D material based devices are examples of this rich space of design architecture 'revolution’.
Tunnel FET (TFET)-based devices have been shown to be a promising option that can achieve Ultra Low Power (ULP) as compared to regular CMOS devices; nevertheless they also have relatively low performance. This PhD would hence study different device architectures and evaluate them in terms of their circuit performance, which aims at circuit-level co-optimization and architectural innovation to avoid the limitations of TFET and ultimately obtain more area and energy efficient digital circuits. This work would require some basic TCAD studies to evaluate the device characteristics, making compact models and designing circuits-/layouts- to study the power-performance characteristics of the proposed device architecture.
Meanwhile, ferroelectrics materials based on doped high-k materials such as hafnium or zirconium oxide are receiving increasing attention as they offer alternative opportunities of steep-slope transistors and supply voltage scaling that complement TFET for ULP options in logic applications. This PhD would hence combine electrical characterization work in laboratory measurements and modeling/simulation efforts to establish well-understood device physics of such devices. The ultimate goal is to generate a physics-based compact model of the ferroelectric devices, and to test the models in representative benchmark circuits to study the power/performance characteristics of digital logic blocks.