RADSTACK-28 - Radiation Tolerant Transistor Stacking in 28 nm CMOS

Current State-of-the-Art Radiation Tolerant circuits are mostly implemented in previous technology nodes. This is mainly caused by the increased sensitivity to Single-Event Effects of deep-submicron technologies, resulting in a limited reliability of the integrated circuit. However, to benefit from the increased frequency performance and the reduced power consumption, advanced radiation tolerant circuit techniques need to be developed. This project focuses on design techniques for radiation tolerant high-voltage and high-power stages in advanced CMOS technology nodes. Both a 28 nm Bulk CMOS and a 28 nm SoI CMOS technology are investigated. After characterizing the technology nodes, techniques will be developed to overcome the impact of both TID and SEEs on high-voltage (stacked) transistor circuits.

Keywords:CMOS

Disciplines:Modelling, Multimedia processing