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A 5GS/s 158.6mW 12b Passive-Sampling 8×-Interleaved Hybrid ADC with 9.4 ENOB and 160.5dB FoMS in 28nm CMOS
Book Contribution - Book Chapter Conference Contribution
This paper presents a 5GS/s 158.6mW 12b Passive-Sampling 8x-Interleaved Hybrid ADC. A power reduction of 2x with a BW larger than 6GHz and a Nyquist SNDR/SFDR of 58.5dB/65.4dB are enabled by: (1) very low resistance/capacitance passive input network; (2) negligible jitter on-chip clock division and distribution; (3) optimized 3-stage Pipelined-SAR sub-ADC hybrid; (4) on-chip sub-ADC/TI analog/digital calibration. The 28nm CMOS prototype achieves a FoMS of 160.5dB and a FoMW of 46.1fJ/conv-step.
Pages: 62 - 64
Number of pages: 3