Patents

A wideband radio-frequency transceiver front-end is provided. The transceiver front-end includes an antenna port and a transmission path coupled to the antenna port comprising a power amplifier and a first matching network. The transceiver front-end further includes a reception path coupled to the antenna port comprising a low noise amplifier and a second matching network. Furthermore, the transceiver front-end includes an impedance inverter coupled in-between the antenna port and the second matching network. Moreover, the transceiver front-end includes a controller comprising switching ...

A wideband radio-frequency transceiver front-end (100) is provided. The transceiver front-end includes an antenna port (101) and a transmission path (110) coupled to the antenna port (101) comprising a power amplifier (111) and a first matching network (113). The transceiver front-end further includes a reception path (120) coupled to the antenna port (101) comprising a low noise amplifier (121) and a second matching network (123). Furthermore, the transceiver front-end includes an impedance inverter (125) coupled in-between the antenna port (101) and the second matching network (123). ...

A wideband radio-frequency transceiver front-end (100) is provided. The transceiver front-end includes an antenna port (101) and a transmission path (110) coupled to the antenna port (101) comprising a power amplifier (111) and a first matching network (113). The transceiver front-end further includes a reception path (120) coupled to the antenna port (101) comprising a low noise amplifier (121) and a second matching network (123). Furthermore, the transceiver front-end includes an impedance inverter (125) coupled in-between the antenna port (101) and the second matching network (123). ...

A semiconductor cell (100, 400) for performing a logic XNOR or XOR operation, the semiconductor cell (100, 400) comprising a memory unit (101, 401) for storing a first operand, an input port unit (102, 402) for receiving a second operand, a switch unit (103 403) configured for implementing the logic XNOR or XOR operation on the stored first operand and the received second operand, and a readout port (104, 404) for providing an output of the logic operation. A plurality of cells may be organized in an array, and one or more of such arrays may be used for implementing a neural network.

A motor operable in resonant mode comprising at least one contact zone (5) with a driven part (6) and a tension element (3) adapted to provide a preload and to constrain movement of at least one electrically excited actuator (2) relative to a stator body (1). The stator body (1) comprises multiple pivoting means (8) adapted to act as pivot points for parts of the stator body located between said pivoting means.

A wideband radio-frequency transceiver front-end is provided. The transceiver front-end includes an antenna port and a transmission path coupled to the antenna port comprising a power amplifier and a first matching network. The transceiver front-end further includes a reception path coupled to the antenna port comprising a low noise amplifier and a second matching network. Furthermore, the transceiver front-end includes an impedance inverter coupled in-between the antenna port and the second matching network. Moreover, the transceiver front-end includes a controller comprising switching ...