Vertical Transistors: a slippery path towards the ultimate CMOS scaling

The semiconductor industry has largely relied on Moore’s law, based on the observation that every new generation of transistors has been better than the previous one in Power, Performance, Area and Cost (PPAC) metrics simultaneously. However, this trend is under a pressure now. The main issue is related to the enormous complexity of both technology and design, which drastically raises not only the manufacturing, but also the R&D costs. Therefore, in order to minimize risks and maximize benefits of a new technology, it is being co-optimized hand in hand with a design relying on this technology.

The scaling of lateral transistors is going to reach its limit soon because it mainly relies on the scaling of contacted gate pitch (CGP), which, in turn, forces the scaling of gate length, S/D spacers and contacts. Reduction of any of these dimensions is undesirable as it leads to poorer electrostatic control, increased parasitic capacitance and increased access resistance, respectively. There are lateral devices, like nanowire-based FETs, which may postpone the problem of CGP budgeting but they cannot solve it.

The focus of this PhD work is on the vertical devices. These devices are less constrained on gate length and spacer thickness as they are oriented vertically and thus should demonstrate better scalability than lateral transistors. We quantify the advantages of the vertical devices in terms of PPA metrics through a holistic benchmark by combining the design techniques and technology limitations which are likely to be in place at the 5nm technology. In order to do this, we perform the layouts analysis, model and evaluate RC parasitics, calibrate compact models to TCAD and experimental data. Afterwards, we run simulations on a ring oscillator level to extract the PPA metrics.

We have not limited ourselves to the conventional MOSFETs only, but we also benchmark vertical III-V heterojunction Tunnel FETs in order to get a better understanding under which conditions the vertical architecture is the most advantageous. This allows us to shed light on the ultimate CMOS scaling and to understand whether the introduction of vertical transistors can enable the next technological nodes.