Method for producing an integrated circuit including a metallization layer comprising low k dielectric material

A method of forming a metallization layer of an IC having a lower via level and an upper trench level is disclosed. In one aspect, the method includes applying a dual damascene process to a stack of two layers. The bottom layer includes a porous low-k dielectric in which the pores have been filled by a template material. The top layer is a template layer. This stack is obtained by depositing a template layer on top of a porous low-k dielectric and annealing in order to let the template material diffuse into the pores of the low-k layer. At the end of the anneal process, a stack of a pore-filled layer and a template layer is obtained. Vias are etched in the low-k layer and trenches are etched in the template layer. The template pore-filling protects the low-k dielectric during plasma etching, metal barrier deposition and metal deposition.

Patent Publication Number: US9941151

Year filing: 2018

Year approval: 2018

Year publication: 2018

Status: Assigned

Technology domains: Semiconductors

Validated for IOF-key: Yes

Attributed to: Associatie KULeuven