Modelling, exploration and technology assessment of steep-subthreshold-slope transistors for N5/N3 CMOS power-performance scaling KU Leuven
For more than half a century, semiconductor integrated circuits (ICs) have evolved with the miniaturization of transistor footprint, the improvement of chip performance and the reduction in operating power, which are collectively referred to as “power-performance-area” (PPA) scaling. Moving on to the sub-deca-nm scaling regime, the main workhorse of the IC industry, Si MOSFET, increasingly struggles to keep up with the unrelenting demand for ...