On the Characterization and Separation of Trapping and Ferroelectric Behavior in HfZrO FET KU Leuven
OAPA N-channel FETs with ferroelectric (FE) HfZrO gate oxide are fabricated, showing steep subthreshold slope under certain conditions. Possible origins of ID-VG hysteresis, the hysteresis vs. subthreshold slope tradeoff, dependence on the bias voltage and temperature and the competition between trapping and FE behavior are reported and discussed. A band of active traps in the ferroelectric layer responsible for charge trapping during device ...