Ferroelectric Switching as an Enabler for Low Power CMOS and Embedded Memory

Korte inhoud:In the modern time electronic industries are looking for cheap, dense, high performance and most importantly energy efficient logic as well as memory technology. As traditional technologies already encountered their limits, industries are looking at the alternatives. In the field of logic; scaling of MOSFETs, that has been the key to improve the performance, has practically stopped due to the fact that power dissipation from the integrated circuit reached a ceiling 100$W/cm^2$. If the scaling is to be continued, the power dissipation per transistor must be reduced at first. However, due to a fundamental limit of physics that came from the Boltzmann distribution, there is a minimum power dissipation from each of the transistors. There was a tremendous effort of introducing new physics into the transistor's operation so that this fundamental limit in the lowest power can be broken. Many device concepts have been investigated before without success. In 2008 it was claimed that so called ``negative capacitance'' exists in ferroelectric materials that is otherwise unstable in nature. Upon proper stabilization though, if ferroelectric is used as a gate oxide of MOSFET, it would provide hysteresis-free steep subthreshold slope in MOSFET's operation, which is the key for reducing their power dissipation. Though the proposal gained a lot of attention it also created a significant controversy in the scientific community. In this thesis at first we thoroughly investigate the negative capacitance theory. We show that the non-linear positive capacitance (PC) of ferroelectrics can explain the steep subthreshold-slope observed in ferroelectric based MOSFETs and often attributed to the existence of a negative capacitance in ferroelectric capacitors. Physically attainable and unattainable regions of the S-shape curve used in the negative capacitance theory are investigated by self-consistently solving Landau-Khalatnikov and Maxwell equations and by experimental validation. Finally, the conditions for attaining a steep steep subthreshold-slope (SS) in ferroelectric (FE) based MOSFETs assuming only positive capacitances are discussed. We show ferroelectric based MOSFET shows a hysteresis vs steep-slope trade-off, that is when the slope the $log I_D-V_G$ curve gets very steep, it shows a large hysteresis and vice-versa. This finding proves that ferroelectric field-effect-transistors (FeFET) unfortunately cannot break the physical limit of MOSFETs power dissipation. On the memory side; as of today 3D-NAND is used for data storage and capacitor based DRAM is used as random access memory. There exist a significant difference in their operating speed in addition to the disadvantage that DRAM is volatile in nature. A potential candidate that can bridge the existing speed gap is named ``storage class memory'' or SCM, which is yet to be commercialized. Although ferroelectric FET cannot attain hysteresis-free steep SS, we show that it is a suitable candidate for SCM. But it requires solution to a key problem, the data retention loss, and we provide this solution in this thesis. We systematically find the dominant mechanism for data retention loss in the FEFET based memory. We show the interaction between trapped charge and the polarization in the ferroelectric oxide determines the memory window as well as retention. Finally, we show the way to optimize their operation so that the maximum memory window and data retention can be obtained.

Jaar van publicatie:2022

Toegankelijkheid:Open